1. Field of the Invention
The present invention relates to a semiconductor device having a structure that memory cell transistors are isolated by an element isolation insulating film thereby to be formed and a method of manufacturing the same.
2. Description of the Related Art
For example, a NOR flash memory is one of memories employing a shallow trench isolation (STI) structure which is one of structures that memory cell transistors are isolated by an element isolation insulating film thereby to be formed. The NOR flash memory employs an arrangement that a contact hole is formed in a drain of each of a number of memory cell transistors so that an electrode is connected to the contact hole. Furthermore, since each memory cell transistor generally employs a lightly doped drain (LDD) structure, a silicon nitride film serving as a spacer is formed on an end face of a gate electrode.
For example, JP-A-2002-158300 discloses the aforementioned arrangement. FIG. 5 of this document shows a silicon nitride film formed as a spacer on a sidewall of a gate electrode and a contact hole which is formed so as to make a contact. This document discloses the following manufacturing process of a semiconductor device. Firstly, on a silicon substrate are deposited a gate insulating film, a first polycrystalline silicon film serving as a floating gate electrode, a first silicon nitride film and a silicon oxide film in this sequence. A photolithography process is carried out to form a resist pattern for formation of an element isolation region. A resist pattern for formation of an element isolation region is then formed by a photolithography process. The silicon oxide film and the first nitride film are etched by a reactive ion etching (RIE) process with the resist pattern serving as a mask. Thereafter, the resist pattern is removed. Subsequently, the first polycrystalline silicon film is etched with the silicon oxide film serving as a mask. Furthermore, the gate insulating film and the silicon substrate are etched so that a trench is formed in the silicon substrate.
Subsequently, a silicon oxide film is formed on an inner wall of the trench. Furthermore, another silicon oxide film is buried in the trench by a high density plasma (HDP) process. A planarizing process is carried out for the buried silicon oxide film by a chemical mechanical polishing (CMP) process with the first silicon nitride film serving as a stopper. The first silicon nitride film is then removed by phosphating. A second polycrystalline silicon film doped with phosphor is deposited by a low pressure chemical vapor deposition (LP-CVD) process. The second polycrystalline silicon film is etched by the RIE process with photoresist serving as a mask.
An oxide-nitride-oxide (ONO) film and a third polycrystalline silicon film doped with phosphor and serving as a control gate are deposited by the LP-CVD process in turn. Successively, a tungsten silicide (WSi) film and a silicon oxide film are deposited by the LP-CVD process in turn. Subsequently, a resist pattern is formed by the photolithography process. The RIE process is then carried out to process the silicon oxide film, the WSi film, the third polycrystalline silicon film, the ONO film, the second polycrystalline silicon film and the first polycrystalline silicon film, whereby a gate electrode is formed.
Subsequently, impurities are introduced into a source/drain region by an ion implantation process, and a second silicon nitride film is deposited by the LP-CVD process. A spacer is then formed by the RIE process. A third silicon nitride film is deposited so as to be superposed on the spacer. An insulating film is deposited by a normal pressure CVD process, and a planarizing process is carried out until the third silicon nitride film is exposed by the CMP process. An interlayer insulating film is formed so as to be buried in a gap between the gate electrodes. Subsequently, the wafer process is completed through the forming of contact holes and the forming of electrode patterns.
In the above-described arrangement, the spacer of silicon nitride film is formed on the sidewall of the gate electrode in order that each memory cell transistor may have the LDD structure. When an employed manufacturing process includes a step of forming an STI structure for isolation of elements after previous formation of a part of the gate structure, the following drawback is found: in the above-described manufacturing process, immediately after formation of the gate electrode, there is a difference in level between the upper surface of the silicon substrate or an active area (an element isolation region) and an upper surface of the STI which is an element isolation region, in a part where a layer serving as a gate electrode has been removed by the etching process. Since a width of the active area is rendered smaller as the design rules are refined more, an amount of part of the sidewall remaining unetched from an upper part to a lower part is increased according to an extent of the difference in the RIE process executed after the third silicon nitride film has been buried. This results in limitations in a contact area in the case where the drain contact of the active area is formed, thereby increasing a drain contact resistance.